#
# Family 10 unit masks
#
# Copyright OProfile authors
# Copyright (c) Advanced Micro Devices, 2006.
# Contributed by Ray Bryant <raybry@amd.com>, and others.
#
name:zero type:mandatory default:0x0
	0x0 No unit mask
name:moesi type:bitmask default:0x1f
	0x10 (M)odified cache state
	0x08 (O)wner cache state
	0x04 (E)xclusive cache state
	0x02 (S)hared cache state
	0x01 (I)nvalid cache state
	0x1f All cache states
name:moess type:bitmask default:0x1e
	0x10 (M)odified cache state
	0x08 (O)wner cache state
	0x04 (E)xclusive cache state
	0x02 (S)hared cache state
	0x01 refill from system
	0x1e All cache states except Invalid
name:fpu_ops type:bitmask default:0x3f
	0x01 Add pipe ops
	0x02 Multiply pipe
	0x04 Store pipe ops
	0x08 Add pipe load ops
	0x10 Multiply pipe load ops
	0x20 Store pipe load ops
name:control_modified type:bitmask default:0x0d
	0x01 Number of times SSE rounding control is changed
	0x04 Number of times x87 rounding control is changed
	0x08 Number of times x87 precision control is changed
name:segregload type:bitmask default:0x7f
	0x01 ES register
	0x02 CS register
	0x04 SS register
	0x08 DS register
	0x10 FS register
	0x20 GS register
	0x40 HS register
name:fpu_instr type:bitmask default:0x0f
	0x01 x87 instructions
	0x02 Combined MMX & 3DNow instructions
	0x04 Combined packed SSE & SSE2 instructions
	0x08 Combined packed scalar SSE & SSE2 instructions
name:fpu_fastpath type:bitmask default:0x07
	0x01 With low op in position 0
	0x02 With low op in position 1
	0x04 With low op in position 2
name:fpu_exceptions type:bitmask default:0x0f
	0x01 x87 reclass microfaults
	0x02 SSE retype microfaults
	0x04 SSE reclass microfaults
	0x08 SSE and x87 microtraps
name:page_access type:bitmask default:0x07
	0x01 DCT0 Page hit
	0x02 DCT0 Page miss
	0x04 DCT0 Page conflict
	0x08 DCT1 Page hit
	0x10 DCT1 Page miss
	0x20 DCT1 Page Conflict
	0x40 Write request
	0x80 Read request
name:mem_page_overflow  type:bitmask default:0x03
	0x01 DCT0 Page Table Overflow
	0x02 DCT1 Page Table Overflow
name:turnaround type:bitmask default:0x3f
	0x01 DCT0 DIMM turnaround
	0x02 DCT0 Read to write turnaround
	0x04 DCT0 Write to read turnaround
	0x08 DCT1 DIMM turnaround
	0x10 DCT1 Read to write turnaround
	0x20 DCT1 Write to read turnaround
name:saturation type:bitmask default:0x0f
	0x01 Memory controller high priority bypass
	0x02 Memory controller low priority bypass
	0x04 DCT0 DCQ bypass
	0x08 DCT1 DCQ bypass
name:slot_missed  type:bitmask default:0x03
	0x01 DCT0 Command slots missed
	0x02 DCT2 Command slots missed
	0x04 DRAM controller interface bypass
	0x08 DRAM controller queue bypass
name:sizecmds type:bitmask default:0x3f
	0x01 non-posted write byte
	0x02 non-posted write dword
	0x04 posted write byte
	0x08 posted write dword
	0x10 read byte (4 bytes)
	0x20 read dword (1-16 dwords)
name:probe type:bitmask default:0xff
	0x01 Probe miss
	0x02 Probe hit
	0x04 Probe hit dirty without memory cancel
	0x08 Probe hit dirty with memory cancel
	0x10 Upstream display refresh/ISOC reads
	0x20 Upstream non-display refresh reads
	0x40 Upstream ISOC writes
	0x80 Upstream non-ISOC writes
name:l2_internal type:bitmask default:0x1f
	0x01 IC fill
	0x02 DC fill
	0x04 TLB reload
	0x08 Tag snoop request
	0x10 Canceled request
name:l2_req_miss type:bitmask default:0x07
	0x01 IC fill
	0x02 DC fill
	0x04 TLB reload
name:l2_fill type:bitmask default:0x03
	0x01 Dirty L2 victim
	0x02 Victim from L1
name:gart type:bitmask default:0xff
	0x01 GART aperture hit on access from CPU
	0x02 GART aperture hit on access from I/O
	0x04 GART miss
	0x08 GART/DEV Request hit table walk in progress
	0x10 DEV hit
	0x20 DEV miss
	0x40 DEV error
	0x80 GART/DEV multiple table walk in progress
name:cpiorequests type:bitmask default:0x08
	0x01 IO to IO
	0x04 IO to Mem 
	0x08 CPU to IO 
	0x10 To remote node
	0x20 To local node
	0x40 From remote node
	0x80 From local node
name:cacheblock type:bitmask default:0x3d
	0x01 Victim Block (Writeback)
	0x04 Read Block (Dcache load miss refill)
	0x08 Read Block Shared (Icache refill)
	0x10 Read Block Modified (Dcache store miss refill)
	0x20 Change to Dirty (first store to clean block already in cache)
name:dataprefetch type:bitmask default:0x03
	0x01 Cancelled prefetches
	0x02 Prefetch attempts
name:memreqtype type:bitmask default:0x83
	0x01 Requests to non-cacheable (UC) memory
	0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory
	0x80 Streaming store (SS) requests
name:systemreadresponse type:bitmask default:0x17
	0x01 Exclusive
	0x02 Modified
	0x04 Shared
	0x10 Data Error
name:mab_um type:exclusive default:0x09
	0x01 Buffer 1
	0x02 Buffer 2
	0x03 Buffer 3
	0x04 Buffer 4
	0x05 Buffer 5
	0x06 Buffer 6
	0x07 Buffer 7
	0x08 Buffer 8
	0x09 Buffer 9
name:page_table_walker_1 type:bitmask default:0x41
	0x01 PDE refill hit in L2 cache
	0x04 PDPE lookup misses in PDC
	0x10 PML4E refill hit in L2 cache
	0x40 PML4E lookup missed in PDC
name:page_table_walker_2  type:bitmask default:0xd1
	0x01 PTE refil hit in L2 cache
	0x10 PDE refill hit in L2 cache
	0x40 PDE lookup missed in PDC
	0x80 PDE lookup in PDC
name:probe_hits_um type:bitmask default:0x03
	0x01 Probe hit Icache
	0x02 Probe hit Dcache
name:cache_cross_invalidates_um type:bitmask default:0x0f
	0x01 DC Invalidates IC, modification of cached instructions, data too close to code
	0x02 DC Invalidates DC, aliasing
	0x04 IC Invalidates IC, aliasing
	0x08 IC Invalidates DC, execution of recently modified code, modified data too close to code
name:tlb_flush type:bitmask default:0x03
	0x01 Actual TLB flushes
	0x02 TLB flush requests
name:l1_dlb_miss_l2_hit type:bitmask default:0x03
	0x01 L2 4K TLB hit
	0x02 L2 2M TLB hit
name:l1_l2_dlb_miss type:bitmask default:0x43
	0x01 4K TLB reload
	0x02 2M TLB reload
	0x40 1G TLB reload
name:ecc type:bitmask default:0x0f
	0x01 Scrubber error
	0x02 Piggyback scrubber errors
	0x04 Load pipe error
	0x08 Store write pip error
name:prefetch type:bitmask default:0x07
	0x01 Load (Prefetch, PrefetchT0/T1/T2)
	0x02 Store (PrefetchW)
	0x04 NTA (PrefetchNTA)
name:locked_instruction_dcache_miss type:bitmask default:0x02
	0x02 Data cache misses by locked instructions
name:quadword_transfer type:bitmask  default:0x01
	0x01 Quadword write transfer
name:cancel_requests type:bitmask default:0x03
	0x01 Total MemCancels seen
	0x02 Read responses successfully canceled
name:write_combine type:bitmask default:0x03
	0x01 Sized Writes not combined
	0x02 Sized writes combined
name:thermal_status  type:bitmask default:0x7c
	0x04 Number of times the HTC trip point is crossed
	0x08 Number of clocks when STC trip point active
	0x10 Number of times the STC trip point is crossed
	0x20 Number of clocks HTC P-state is inactive
	0x40 Number of clocks HTC P-state is active
name:mem_control_request type:bitmask default:0x78
	0x08 32 Bytes Sized Writes
	0x10 64 Bytes Sized Writes
	0x20 32 Bytes Sized Reads
	0x40 64 Byte Sized Reads
name:srifull_cycles_1 type:bitmask default:0x5f
	0x01 Request
	0x02 Posted request
	0x04 Response
	0x08 Display refresh
	0x10 Request data
	0x40 Response data
name:srifull_cycles_2 type:bitmask default:0x3f
	0x01 Upstream request
	0x02 Upstream posted request
	0x04 Display refresh
	0x08 Probe
	0x10 Downstream request
	0x20 Downstream posted request
name:xbarfull_cycles type:bitmask default:0x15
	0x01 Request
	0x04 Display Refresh
	0x10 Request data
name:mctfull_cycles type:bitmask default:0x4c
	0x04 Response
	0x08 Probe
	0x40 Response data
name:htfull type:bitmask default:0xdf
	0x01 Request buffer
	0x02 Posted request buffer
	0x04 Response buffer
	0x08 Probe buffer
	0x10 Request/posted request data buffer
	0x40 Response data buffer
	0x80 Sublink Mask
name:httransmit type:bitmask default:0xbf
	0x01 Command DWORD sent
	0x02 Address extension DWORD sent
	0x04 Data DWORD sent
	0x08 Buffer release DWORD sent
	0x10 Nop DW send, idle
	0x20 Per packet CRC sent
	0x80 SubLink Mask
name:memory_type_request type:bitmask default:0xf3
	0x01 UC
	0x02 WC
	0x10 WT
	0x20 WP
	0x40 WB
	0x80 Streaming store
name:instr_fetch type:bitmask default:0x0f
	0x01 All stalls except stalls specified the other three unitmasks
	0x02 Stalls caused when a branch is written to the branch array
	0x04 Stalls caused when the branch array is full
	0x08 Stalls caused when the instruction buffer is full
name:cpu_apic_2 type:bitmask default:0x0f
	0x01 Local APIC reads
	0x02 Local APIC writes
	0x04 APIC TPR writes
	0x08 Fast APIC TPR writes
name:lock_ops type:bitmask default:0x07
	0x01 Number of locked instructions executed
	0x02 Cycles in speculative phase
	0x04 Cycles in non-speculative phase
	
